The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) manufacturing processes. More particularly, the present invention relates to hydrogen barrier encapsulation techniques for the control of hydrogen induced degradation of ferroelectric memory devices, in particular with respect to multi-level metal IC processing.
Certain memory devices, such as the FRAM(copyright) (FRAM is a registered trademark of Ramtron International Corporation, Colorado Springs, Colo.) family of solid state, random access memory integrated circuits, provide non-volatile data storage through the use of a ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value representative of a logic level xe2x80x9conexe2x80x9d or xe2x80x9czeroxe2x80x9d. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
A hysteresis curve, wherein the abscissa and ordinate represent the applied voltage (xe2x80x9cVxe2x80x9d) and resulting polarization (xe2x80x9cQxe2x80x9d) states respectively, may be plotted to represent the response of the polarization of a ferroelectric capacitor to the applied voltage. A more complete description of this characteristic hysteresis curve is disclosed, for example, in U.S. Pat. Nos. 4,914,627 and 4,888,733 assigned to the assignee of the present invention, the disclosures of which are herein specifically incorporated by this reference.
Data stored in a ferroelectric memory cell is xe2x80x9creadxe2x80x9d by applying an electric field to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and produce either a logic xe2x80x9conexe2x80x9d or xe2x80x9czeroxe2x80x9d at the IC output pins provided that xe2x80x9cQxe2x80x9d is sufficiently large. In a conventional two transistor/two capacitor (xe2x80x9c2C/2Txe2x80x9d) ferroelectric memory cell, (one transistor/one capacitor xe2x80x9c1T/1Cxe2x80x9d devices have also been described) a pair of two data storage elements are utilized, each polarized in opposite directions. To xe2x80x9creadxe2x80x9d the state of a 2T/2C memory cell, both elements are polarized in the same direction and the sense amps measure the difference between the amount of charge transferred from the cells to a pair of complementary bit lines. In either case, since a xe2x80x9creadxe2x80x9d to a ferroelectric memory is a destructive operation, the correct data is then restored to the cell during a precharge operation.
In a simple xe2x80x9cwritexe2x80x9d operation, an electric field is applied to the cell capacitor to polarize it to the desired state. Briefly, the conventional write mechanism for a 2T/2C memory cell includes inverting the dipoles on one cell capacitor and holding the electrode, or plate, to a positive potential greater than the coercive voltage for a nominal 100 nanosecond (xe2x80x9cnsec.xe2x80x9d) time period. The electrode is then brought back to circuit ground for the other cell capacitor to be written for an additional nominal 100 nsec. In any event, the switching polarization (xe2x80x9cQswxe2x80x9d, where Qsw=2Pr, the remnant polarization) of the device must be sufficiently large for the signal presented to the sense amplifiers to be accurately read or the performance of the device is severely degraded should Qsw be too low for reliable operation.
It has been observed that when a ferroelectric capacitor is exposed to hydrogen species, the ferroelectric properties of the capacitor are severely degraded. The rate at which this degradation occurs is a function of the flux of hydrogen which comes in direct contact with the ferroelectric capacitor and temperature although the type of hydrogen species, (i.e. monatomic vs. diatomic) is also a factor. Diffusion of hydrogen through conductive and non-conductive layers surrounding the ferroelectric capacitor is a function of hydrogen concentration, temperature, time and the diffusivity of hydrogen through a given material in accordance with Fick""s laws of diffusion. As a consequence, control of these factors can be used to ameliorate or reduce ferroelectric device degradation due to the presence of hydrogen.
Following the formation of the ferroelectric capacitor structures on an integrated circuit (xe2x80x9cICxe2x80x9d) device, some type of electrical interconnect is required to couple the transistor and capacitor components of the IC device. Typical IC interconnect materials include alloys of aluminum, tungsten and oxide non-conductive layers. Most of the industry standard process steps used for such interconnect processing contain hydrogen species or require process temperatures at or above 400xc2x0 C. or both.
Recently, two mechanisms for hydrogen induced degradation in IC devices have been identified:
1) Hydrogen generated external to the die due to process steps which contain hydrogen (either deliberately introduced into the process-step or as a byproduct of the process step). These process steps may include chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) of oxides or refractory materials, anneals or etch process steps; and
2) Hydrogen generated within the body or structure of the die. For example, water adsorbed within oxide layers has been shown to diffuse through the oxide layer at fairly low temperatures (xcx9c400xc2x0 C.) and react with metals within the die structure which cause the dissociation of the water molecule and subsequently generate hydrogen species which in turn degrade ferroelectric device performance.
Multilevel metal processes for standard memory, embedded or logic devices using design rules of 0.5 xcexcm or smaller commonly include process steps such as tungsten plug deposition, high density plasma (xe2x80x9cHDPxe2x80x9d, silane based) interlevel oxide deposition or plasma tetraethyloxysilicate (xe2x80x9cTEOSxe2x80x9d) oxide deposition, chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) for planarization of oxide or tungsten plug layers and hot metal reflow (420xc2x0 C. up to 520xc2x0 C. wafer substrate temperature) aluminum deposition. All of these process steps generate hydrogen either directly or through various secondary mechanisms. CVD tungsten plug deposition, for example, uses roughly 3% (or higher) hydrogen (at 400xc2x0 C. to 500xc2x0 C.) for the carrier gas, and HDP oxide deposition uses silane which reacts to form SIO2, water and hydrogen. CMP utilizes a water slurry which causes water adsorption into the oxide films. Subsequently, during any process step using temperatures of 400xc2x0 C. or greater (tungsten plug deposition, interlevel dielectric (xe2x80x9cILDxe2x80x9d) oxide deposition or hot aluminum reflow deposition), water will diffuse through the oxide layer and disassociate at metal interfaces to form hydrogen and oxygen as previously noted.
Therefore, in order to successfully integrate ferroelectric capacitors with multilevel metal process steps it is necessary to either: 1) remove the hydrogen from the multilevel metal process steps altogether; or 2) to make the ferroelectric device more immune to hydrogen degradation.
Completely removing the hydrogen from industry standard process steps would, naturally, require a great deal of new process development. If such were even possible to achieve, it would likely result in many non-standard processes and equipment configurations which would increase the cost and complexity of manufacturing ferroelectric IC""s.
A more desirable method, therefore would be to somehow render the ferroelectric capacitor more immune to hydrogen degradation. Improving the hydrogen immunity of ferroelectric capacitors, however, has long been a major impediment to ferroelectric process integration. In this regard, various methods have been reported including doping the ferroelectric material itself to make it less susceptible to hydrogen damage (often at the compromise of other ferroelectric electrical properties) or the use of compound or exotic electrode materials. Several of these methods have been successful in somewhat reducing hydrogen induced degradation, but none have made the ferroelectric capacitor completely immune to the multiple process steps required for multilevel metal processing.
Several authors have heretofore reported the use of a hydrogen barrier layer used to shield the ferroelectric capacitor from hydrogen damage during subsequent processing. Although a number of materials have proven useful as hydrogen barrier materials, no structure has as yet been proposed or demonstrated which adequately seals the ferroelectric capacitor from hydrogen damage. In this regard, one known approach includes the use of an alumina (Al2O3) or rutile (TiO2) barrier over a lead zirconium titanate (PZT) capacitor where the hydrogen barrier material is first placed over the side walls and top of the ferroelectric cap structure. (See IEDM 1997, structures proposed by Samsung using Al2O3; p. 617 and Sharp using TiO2; p 609). Subsequently, a contact opening is formed through the barrier material in order to provide an interconnect to the ferroelectric capacitor top electrode. However, once such a contact opening is made through the hydrogen barrier material, it can no longer effectively prevent the flux of hydrogen to the ferroelectric capacitor. Stated another way, once the contact opening is made, the barrier effects are essentially rendered useless and during subsequent processing steps, the rate of degradation due to hydrogen damage, while somewhat reduced, is never totally eliminated due to the fact that a serious flaw exists in the structure in the form of the hole through the barrier layer. This hydrogen degradation results in a Qsw switching loss which is a function of the top electrode contact (xe2x80x9cTECxe2x80x9d)/top electrode area (xe2x80x9cTExe2x80x9d) area ratio. As a result, although a barrier layer may somewhat improve the switched charge of the ferroelectric capacitor, switched charge degradation as a function of the TEC/TE area ratio still occurs.
In another work, (c.f. U.S. Pat. No. 5,554,559) a blanket hydrogen barrier layer is used over the entire ferroelectric capacitor after formation of the top electrode contact. However, this does not ultimately protect the capacitor from water vapor or hydrogen attack from the oxide layers underneath the silicon nitride blanket layer. Also, a sidewall contact is used to connect the ferroelectric capacitor to the drain of the pass transistor. This structure may be problematic in a manufacturing environment.
In yet another work, (c.f. U.S. Pat. No. 5,536,672) a blanket TiO2/Si3N4 layer is used under the ferroelectric stack to block lead in the PZT capacitor from diffusing into the BPSG layer overlying the CMOS transistors. Nevertheless, this structure has made no provision for blocking hydrogen from diffusing through the top electrode contact region during subsequent processing.
In accordance with the technique of the present invention, an improved hydrogen barrier structure is advantageously utilized in order to completely encapsulate the ferroelectric capacitor and protect it from hydrogen or moisture during subsequent process steps. Subsequent process steps may include many different combinations of interconnect steps which are well known in semiconductor IC processing, including, for example, the sputter deposition of titanium (Ti), titanium nitride (TiN), or aluminum alloys, the CVD deposition of oxides, nitrides, or tungsten, CMP polishing of oxide and conductive layers, the etching of oxides and conductive film layers and the like. In accordance with specific implementations of the technique of the present invention disclosed hereinafter, four representative interconnect structures are illustrated integrated in conjunction with an encapsulated ferroelectric capacitor, although the technique is similarly applicable to many other interconnect schemes as well.
In accordance with the specific embodiments of the present invention disclosed herein an important feature is the addition of a hydrogen barrier layer over the ferroelectric capacitor top electrode contact. This barrier layer effectively acts as a xe2x80x98corkxe2x80x99 to seal the top of the encapsulated hydrogen barrier structure, rendering the entire structure highly resistant to hydrogen penetration. Materials for forming the xe2x80x9ccorkxe2x80x9d material can be selected from any of a number of materials or combinations of materials commonly used in the semiconductor industry which demonstrate some barrier properties to hydrogen. These include, but are not limited to, silicon nitride (deposited by low temperature plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d), sputter deposition or other techniques), titanium nitride, alumina (Al2O3) TiO2 and other hydrogen barrier forming materials.
Although the barrier material used in the preferred embodiment of this work, silicon nitride (Si3N4), is a very good hydrogen barrier, it is still not a perfect hydrogen barrier. Given an adequately long time at elevated temperature, some hydrogen will eventually diffuse through silicon nitride or other hydrogen barrier materials. Thicker barrier layers may be used to limit the amount of hydrogen diffusion through these layers. However thicker barrier films will reduce manufacturing throughput and may compromise the manufacturability and performance of the ferroelectric product. Consequently, a wise choice of process flow and minimal time at elevated process temperature for subsequent process steps will allow use of minimal barrier thicknesses and facilitate an optimized manufacturing process which may advantageously include a forming gas (or hydrogen) anneal process step upon the completed integrated circuit structure.
Particularly disclosed herein is an integrated circuit device and a process for forming the same comprising a plurality of memory cells, each of the memory cells comprising at least one capacitor. The capacitor includes a bottom electrode overlying an insulating layer; a dielectric layer overlying the bottom electrode; a top electrode overlying the dielectric layer; a contact providing electrical coupling to the top electrode; and a hydrogen barrier material formed on an upper surface of the contact.
Further disclosed herein is an integrated circuit device, including at least one capacitor integrated thereon, and a process for forming the same which comprises: a substrate having a major surface thereof; a first hydrogen barrier material layer overlying the substrate; a first insulating layer overlying the first hydrogen barrier material layer; a first electrode layer overlying the first insulating layer and substantially coextensive therewith; a dielectric layer overlying the first insulating layer; a second electrode layer overlying-the dielectric layer; a contact electrically adjoining the second electrode layer at an upper surface thereof; a second insulating layer overlying exposed portions of the first electrode layer, the dielectric layer and the second electrode layer adjacent the contact; a second hydrogen barrier material layer contiguous with the first hydrogen barrier material layer and overlying the second insulating layer; and an additional hydrogen barrier material layer overlying the contact.